Difference between revisions of "RISC-V"
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=== The RISC-V processor ISA === | === The RISC-V processor ISA === | ||
| − | The RISC-V Processor is a RISC based architecture, with less instructions than most other RISC processors. For example, there is no GT (>) or GE (>=) hardware instructions, only LT (<) or LE (<=) instruction, but the RISC-V assembly language support GT and GE, and switch it to LT/LE by switching also registers to keep the test as needed. | + | The RISC-V Processor is a RISC based architecture, with less instructions than most other RISC processors. For example, there is no GT (>) or GE (>=) hardware instructions, only LT (<) or LE (<=) instruction, but the RISC-V assembly language support GT and GE, and switch it to LT/LE by switching also registers to keep the test as needed. The same way, several instructions are supported in RISC-V assembly language that doesn't actually exists as code machine instructions. |
One of the main goals of the specifications is to have modularity with high granularity. So bitwise operators, multiplications/divisions, vector instructions for example are on different optional extensions, that can be implemented or not by RISC-V processor makers, reducing the total number of transistors depending on processor usage. Each extension have its own letter added in the name of the processor. | One of the main goals of the specifications is to have modularity with high granularity. So bitwise operators, multiplications/divisions, vector instructions for example are on different optional extensions, that can be implemented or not by RISC-V processor makers, reducing the total number of transistors depending on processor usage. Each extension have its own letter added in the name of the processor. | ||
The specifications are all available on the risc-v.org site: https://riscv.org/technical/specifications/ | The specifications are all available on the risc-v.org site: https://riscv.org/technical/specifications/ | ||
| + | |||
| + | === Tools === | ||
| + | * GNU tools contains both RISC-V 32 and 64bits compiler (GCC), assembler (gnu-binutils) and debugger (GDB), they are available for native or cross-compiling on most GNU/Linux distribution. | ||
| + | |||
| + | * [https://github.com/theandrew168/bronzebeard Bronzebeard] is a standalone assembler for developing bare metal RISC-V programs. | ||
| + | |||
| + | === Test it === | ||
| + | If you don't have one of those cheap boards, you can still test RISC-V assembly on an emulator. | ||
| + | Qemu allow to execute RISC-V application or systems on any kind of architectures. You can use the same tricks than used on x86 to reduce the binary size of the ELF binary format made with GNU tools. | ||
| + | |||
| + | The main author of Qemu also made [https://bellard.org/tinyemu/ TinyEmu], a RISC−V only tiny emulator, it already has WASM ports, so you can play with it on the web. | ||
Revision as of 13:46, 29 September 2021
Introduction
RISC-V is an open and free standard or RISC ISA. It exists in 32,64 and still in draft stage, 128 bits wide versions. There are lot of free or non free implementations. You can find software, FPGA, or ASIC implementations on most codeforges like Github, Gitlab, Gitea, etc... Several research institute around the world also opened their own versions.
The RISC-V processor ISA
The RISC-V Processor is a RISC based architecture, with less instructions than most other RISC processors. For example, there is no GT (>) or GE (>=) hardware instructions, only LT (<) or LE (<=) instruction, but the RISC-V assembly language support GT and GE, and switch it to LT/LE by switching also registers to keep the test as needed. The same way, several instructions are supported in RISC-V assembly language that doesn't actually exists as code machine instructions.
One of the main goals of the specifications is to have modularity with high granularity. So bitwise operators, multiplications/divisions, vector instructions for example are on different optional extensions, that can be implemented or not by RISC-V processor makers, reducing the total number of transistors depending on processor usage. Each extension have its own letter added in the name of the processor.
The specifications are all available on the risc-v.org site: https://riscv.org/technical/specifications/
Tools
- GNU tools contains both RISC-V 32 and 64bits compiler (GCC), assembler (gnu-binutils) and debugger (GDB), they are available for native or cross-compiling on most GNU/Linux distribution.
- Bronzebeard is a standalone assembler for developing bare metal RISC-V programs.
Test it
If you don't have one of those cheap boards, you can still test RISC-V assembly on an emulator. Qemu allow to execute RISC-V application or systems on any kind of architectures. You can use the same tricks than used on x86 to reduce the binary size of the ELF binary format made with GNU tools.
The main author of Qemu also made TinyEmu, a RISC−V only tiny emulator, it already has WASM ports, so you can play with it on the web.
